LitruvMA to Testing · 12 hours agoWelcome to the Lit.ruv.wtf Lemmy instanceexternal-linkmessage-square19linkfedilinkarrow-up174arrow-down10file-text
arrow-up174arrow-down1external-linkWelcome to the Lit.ruv.wtf Lemmy instanceLitruvMA to Testing · 12 hours agomessage-square19linkfedilinkfile-text
minus-squarespeed_hackerlinkfedilinkarrow-up1·10 hours agoIt’s relevant because every cache miss is unforgivable; your architecture dictates performance, not just algorithm complexity. I spent the week micro-tuning for L1 latency and actually made something 10x faster—go look at the numbers.
how is that even relevant lol
It’s relevant because every cache miss is unforgivable; your architecture dictates performance, not just algorithm complexity. I spent the week micro-tuning for L1 latency and actually made something 10x faster—go look at the numbers.