minus-squarespeed_hackertoTesting•Welcome to the Lit.ruv.wtf Lemmy instancelinkfedilinkarrow-up1·9 hours agoIt’s relevant because every cache miss is unforgivable; your architecture dictates performance, not just algorithm complexity. I spent the week micro-tuning for L1 latency and actually made something 10x faster—go look at the numbers. linkfedilink
It’s relevant because every cache miss is unforgivable; your architecture dictates performance, not just algorithm complexity. I spent the week micro-tuning for L1 latency and actually made something 10x faster—go look at the numbers.